As the size of the chip increases and the dimension of the transistors moves to nanometer range, process and environment variations become more and more important for the performance of the VLSI design. Variations are usually categorized into global variation (also known as chip-to-chip variation) and local variation (also known as on-chip variation, or OCV). In cutting-edge VLSI designs that are built-upon advanced manufacturing process node, the ratio of local on-chip variation over total variations keep increasing.
In static timing analysis, OCV derating techniques are widely used to model on-chip variations. One problem with OCV derating is that it uses a single number to model all on-chip variations, and consequently introduces more and more pessimism in the advanced technology nodes. To remove some pessimism, Location-based OCV (LOCV) and its derivatives were proposed to introduce logic-depth and location aware OCV techniques (see Hong, J.; Huang, K.; Pong, P.; Pan, J. D.; Kang, J.; Wu, K. C., “An LLC-OCV Methodology for Static Timing Analysis”, VLSI Design, Automation and Test, 2007.
On the other hand, a lot of research has also been done on statistical static timing analysis (SSTA) to address the variation impact (see Hongliang Chang, Sachin S. Sapatnekar: Statistical Timing Analysis Considering Spatial Correlations Using a Single Pert-like Traversal. ICCAD 2003:621-626; Yaping Zhan, Andrej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma: “Correlation-aware statistical timing analysis with non-Gaussian delay distributions” DAC 2005:77-82).
SSTA is a promising methodology for modeling variations. However, the high cost of its input data preparation, including statistical library characterization and statistical extraction, impedes a rapid, wide adoption of the technology.
Parametric on-chip variation (POCV) is a methodology that provides an on-chip variation model that is derived from statistical static timing methodologies, but that does not require expensive statistical library characterization and statistical RC parasitic extraction (see Ayhan Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik, “A parametric approach for handling local variation effects in timing analysis”, IEEE/ACM International Conference on Computer Aided Design (ICCAD)”, November 2009). However, POCV as taught therein stopped short of addressing the excessive computing resources typically required when processing random variations. The need remains for a method of on-chip variation modeling in statistical timing analysis that is sufficiently low cost so as to encourage widespread and rapid adoption, where cost factors include input data preparation as well as computing resources.